1. Field of the Invention
The present invention relates to memory devices. More specifically, the present invention relates to static random access memory (RAM) cells.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
2. Description of the Related Art
As described in S. M. Sze, VLSI Technology,McGraw-Hill, NY, pp. 473-478 (1983) a conventional four-transistor (4T) RAM cell consists of a two cross-coupled transistors, each with a resistive-load, plus two access transistors (also known as word-line, transfer gate, or pass-gate transistors). The two cross-coupled transistors are known as driver or pull-down transistors. As illustrated in FIG. 1, two state nodes exist in the conventional cell, node 1 and node 2. Node 1 connects one load, the source of one pass-gate transistor, T2, the drain of one driver transistor, T1, and the gate of the other driver transistor T3. Node 2 connects the other load, the source of the other pass-gate transistor, T4, the drain of T3, and the gate of T1.
In static RAM cells, data retention reliability is a direct function of cell stability and noise margin. Noise margin is measured by how well one driver transistor, say T1, holds a low logic level. This low level must remain below the threshold voltage of the other driver transistor, T3, to insure that T3 is off, and therefore to prevent the cell from flipping. If node 1 exceeds the threshold of T3, then T3 will conduct and easily degrade the high level on node 2.
The worst case for cell logic low level is during the time the word line is being selected and the transfer gate, T2, begins to pull up against T1. A good logic low on node 1, and therefore good noise margin and stability, is achieved by making T2 small in size (width to length) and therefore high in resistance with respect to T1.
However, the speed with which the cell develops differential to a sense amplifier is determined by the rate at which the bit line capacitance is discharged through the T2, T1 pair and therefore by the size of the transfer gate, T2. (The sense amp is a differential amplifier whose inputs are BIT and BIT.) For high cell pull current, T2 should be sized large with respect to T1. High cell pull current results in fast cell read access time, since that current is responsible for slewing the bit-line capacitance and developing differential to the sense amplifier.
These conflicting transfer gate sizing requirements for speed and stability limit the ultimate performance of the traditional cell configuration. The cell must be designed to meet a minimum stability level for reliable operation over process variations and operating conditions. Once stability is designed for, cell pull current is fixed and cannot be increased.
This problem is exacerbated in enhancement/depletion mode GaAs RAM design, since the enhancement FET threshold voltage has a strong dependence on temperature and drops significantly at elevated operating temperatures. This forces the transfer gate to further decrease in size to maintain cell stability over wide temperature ranges. This decreased size slows the cell read access time.
Thus, the conventional approach is drastically limited in flexibility to address this tradeoff of speed versus stability. Many static RAM manufacturers have simply decreased the pull-down driver to transfer gate ratio to get improved cell speed. However, these designs are, as a result, plagued with marginally stable cells and "weak bits" which are hard to detect and test.
Another alternative to speeding up the cell is to maintain an adequate cell ratio for stability and then scale FET sizes up to get increased cell pull current. However, this increases chip size and power and is only marginally effective, since the load capacitance the cell must drive scales with cell size as well. There may be no real improvement in cell speed by this method.
Thus, there has been a need for a design which offers high speed and stability in a GaAs static RAM cell, without compromise of one or the other property. This need is addressed by U.S. Pat. No. 4,995,000 issued Feb. 19, 1991 to W. C. Terrell entitled Static RAM Cell with High Speed and Stability. This reference discloses an FET-based static RAM cell design which offers both high speed and stability through the use of isolation devices. The isolation devices allow the pulldown devices with the cell to pull substantially more current while maintaining a good low level on the cross-coupled pair. This keeps the gates of the transistors in the cross-coupled pair as negative as possible which, in turn, reduces subthreshold current (leakage) therethrough. Hence, stability requirements are decoupled from cell pull current requirements.
However, with the Terrell design, the load devices are connected to the state nodes where node information is stored as voltages. When the cell is written, current must be sunk through the isolation device to an output line. If the resistance of the isolation device is large (which is desirable for stability), then a large voltage is generated across the isolation device making it difficult to pull the node with state low enough to flip the cell. This impedes the speed of operation of the device.
Thus, while the Terrell patent provides for significant improvements in the art, there remains an ongoing need for further improvements in static RAM cell design.